1. Field of the Invention
The present invention relates to a process flow for forming a contact layer including solder bumps, which is used to provide contact areas for directly attaching an appropriately formed package or carrier substrate to a die carrying an integrated circuit.
2. Description of the Related Art
In manufacturing integrated circuits, it is usually necessary to package a chip and provide leads and terminals for connecting the chip circuitry with the periphery. In some packaging techniques, chips, chip packages or other appropriate units may be connected by means of solder balls, formed from so-called solder bumps, that are formed on a corresponding layer, which will be referred to herein as a contact layer, of at least one of the units, for instance on a dielectric passivation layer of the microelectronic chip. In order to connect the microelectronic chip with the corresponding carrier, the surfaces of two respective units to be connected, i.e., a microelectronic chip comprising, for instance, a plurality of integrated circuits, and a corresponding package, have formed thereon adequate pad arrangements to electrically connect the two units after reflowing the solder bumps provided at least on one of the units, for instance on the microelectronic chip. In other techniques, solder bumps may have to be formed that are to be connected to corresponding wires, or the solder bumps may be brought into contact with corresponding pad areas of another substrate acting as a heat sink. Consequently, it may be necessary to form a large number of solder bumps that may be distributed over the entire chip area, thereby providing, for example, the I/O capability required for modern microelectronic chips that usually include complex circuitry, such as microprocessors, storage circuits and the like and/or include a plurality of integrated circuits forming a complete complex circuit system.
In order to provide hundreds or thousands of mechanically well-fastened solder bumps on corresponding pads, the attachment procedure of the solder bumps requires a careful design since the entire device may be rendered useless upon failure of only one of the solder bumps. For this reason, one or more carefully chosen layers are generally placed between the solder bumps and the underlying substrate or wafer including the pad arrangement. In addition to the important role these interfacial layers, herein also referred to as underbump metallization layers, may play in endowing a sufficient mechanical adhesion of the solder bump to the underlying pad and the surrounding passivation material, the underbump metallization has to meet further requirements with respect to diffusion characteristics and current conductivity. Regarding the former issue, the underbump metallization layers have to provide an adequate diffusion barrier to prevent the solder material, frequently a mixture of lead and tin, from attacking the chip's underlying metallization layers and thereby destroying or negatively affecting their functionality. Moreover, migration of solder material, such as lead, to other sensitive device areas, for instance into the dielectric, where a radioactive decay of lead may also significantly affect the device performance, has to be suppressed highly efficiently by the underbump metallization. Regarding current conductivity, the underbump metallization, which serves as an interconnect between the solder bump and the underlying metallization layer of the chip, has to exhibit a thickness and a specific resistance that does not inappropriately increase the overall resistance of the metallization pad/solder bump system. In addition, the underbump metallization will serve as a current distribution layer during electroplating of the solder bump material. Electroplating is presently the preferred deposition technique, since physical vapor deposition of solder bump material, which is also used in the art, requires a complex mask technology in order to avoid any misalignments due to thermal expansion of the mask while it is contacted by the hot metal vapors. Moreover, it is extremely difficult to remove the metal mask after completion of the deposition process without damaging the solder pads, particularly when large wafers are processed or the pitch between adjacent solder pads decreases.
Although a mask is also used in the electroplating deposition method, this technique differs from the evaporation method in that the mask is created using photolithography to thereby avoid the above-identified problems caused by physical vapor deposition techniques. However, electroplating requires a continuous and uniform current distribution layer adhered to the substrate that is mainly insulative, except for the pads on which the solder bumps have to be formed. Thus, the underbump metallization also has to meet strictly set constraints with respect to a uniform current distribution as any non-uniformities during the plating process may affect the final configuration of the solder bumps and, after reflowing the solder bumps, of the resulting solder balls in terms of, for instance, height non-uniformities, which may in turn translate into fluctuations of the finally obtained electric connections and the mechanical integrity thereof.
After the formation of the solder bumps, the underbump metallization has to be patterned to electrically insulate the individual solder bumps from each other. The resulting islands of underbump metallization, obtained by highly complex isotropic etch processes including wet chemical and/or electrochemical etch procedures with complex chemistry, also significantly determine the functionality and configuration of the solder balls, since the etch chemistry may result in under-etching of the solder bumps which act as a mask during the wet chemical etch process. Consequently, a varying degree of under-etch may result in a varying size of the resulting underbump metallization islands associated with each solder bump, thereby significantly affecting the configuration of the solder ball after reflow as the highly wettable underbump metallization substantially determines the flow behavior of the solder material and thus the finally obtained size and hence the height of the solder ball. Moreover, due to the complexity of the wet etch chemistry and the etch recipes, a plurality of cleaning steps are required during the patterning of the underbump metallization, thereby contributing to overall production cost. After patterning the underbump metallization, a final cleaning process is performed to remove contaminants and byproducts of the preceding etch processes from the solder bump prior to reflowing the solder bump. After reflow and testing the solder balls, the device may be assembled by attaching it to a correspondingly designed carrier.
FIG. 1 depicts in more detail a typical conventional process flow 100 for forming a contact layer and attaching complex microelectronic chips directly with a carrier substrate. In step 110, an underbump metallization layer 114 may be formed on a passivation layer 113 formed above a substrate 111, wherein the passivation layer 113 comprises an opening to expose a contact pad 112. Typically, the underbump metallization layer 114 is comprised of a plurality of individual layers, such as a titanium layer, a titanium/tungsten layer and the like, for providing the required adhesion characteristics followed by a barrier layer, such as a chromium, a chromium/copper layer, a nickel layer, a nickel/vanadium layer, providing the diffusion blocking effect, followed, for instance, by a final copper layer that may serve as a current distribution layer. Hereby, the thicknesses of the individual layers of the underbump metallization 114 are in general chosen to optimize the stress/thickness product, the diffusion properties and the mechanical integrity of the entire layer stack. The individual layers of the underbump metallization layer 114 are typically formed by sputter deposition or chemical vapor deposition, depending on the type of material used.
Next, in step 120, a lithography process is performed to form a resist mask 121 above the underbump metallization layer 114, wherein the resist mask 121 has an opening formed therein to define the dimensions and the shape of a solder bump to be formed therein. In step 130, a solder bump 131 is formed by means of the resist mask 121, for instance by electroplating, wherein at least the uppermost layer of the underbump metallization layer 114 acts as an efficient current distribution layer, as already previously described. Thereafter, in step 140, the resist mask 121 is removed by well-known wet chemical strip methods or dry etch techniques. Next, in step 150, the underbump metallization layer 114 is patterned by means of wet chemical or electrochemical etch techniques, which require a highly complex etch chemistry owing to the variety of materials, which individually may per se require complex etch procedures. Moreover, due to the complexity of process steps and etch chemistries, several cleaning steps are usually required for removing any byproducts created during the individual etch procedures. Due to the isotropic nature of these etch processes, a certain degree of under-etching, indicated as 151, may occur which may be dependent on device specific characteristics, such as pattern density, uniformity of the individual etch and clean processes and the like. Especially wet chemical or electrochemical etch processes and corresponding clean processes associated with the patterning of chromium and any alloys thereof require highly sophisticated techniques to ensure that substantially no residuals are left on the passivation layer 121 to keep yield losses due to bump shortage at a low level. Moreover, since the degree of under-etching 151 significantly affects the configuration of the finally obtained bump characteristics, such as bump height, co-planarity and the like, strict layout restrictions on substrate level and even on die level for positioning the solder bumps 131 are to be met to enhance the overall uniformity of the wet or electrochemical etch process 150.
Next, in step 160, a final cleaning step is performed to remove contaminants and byproducts from the preceding step 150 from the solder bump 131, thereby preparing it for a following reflow process in step 170 to form a rounded solder ball 171. During reflow, the solder material, especially any tin contained therein, may form an intermetallic phase with the copper of the uppermost sub layer of the underbump metallization layer 114, thereby creating a reliable metallization interface. In step 180, the solder balls 171 may be tested in view of electrical and/or mechanical functionality. Finally, in step 190, the device represented by the substrate 111 may be assembled, that is, may be attached to a corresponding substrate having formed thereon respective contact pads, which may be brought into contact with the solder balls 171 by reflowing the solder balls 171.
As a result, in the typical conventional process flow 100, a plurality of highly complex steps are involved which require sophisticated process and chemistry control, thereby adding to production cost while at the same time rendering the process flow 100 less flexible, especially in view of reducing the size and pitch of solder bumps as may be necessary in highly complex microelectronic chips.
In view of the situation described above, there is a need for an improved technique for forming a contact layer including solder bumps, wherein one or more of the problems identified above are removed or the effects thereof at least significantly reduced.